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Filtering by: Advisor Hanumolu, Pavan Kumar

Low noise clocking for high speed serial links

A Study of Sample-and-Hold Circuit with Application to Beat Test and Dual-Slope ADC

Design of a Digital to Analog Converter for Implementation in an On‐Chip Calibration I...

Low power design techniques for high speed pipelined ADCs

Design of a Process Independent Tool for the Creation of On-Chip Serial Test Interfaces

Design and Implementation of an Automated Star Tracking System

Design techniques for high efficiency LED drivers

Design techniques for wideband low-power Delta-Sigma analog-to-digital converters

Low-power techniques for supply-noise mitigation in phase-locked loops

Design techniques for high-performance digital PLLs and CDRs

Time-based analog signal processing

Dual referencing guidelines to minimize power delivery noise coupling

Design techniques for successive approximation register analog-to-digital converters

Digitally assisted control techniques for high performance switching DC-DC converters

Design of a low jitter digital PLL with low input frequency

Performance enhancement techniques for low power digital phase locked loops

Semi-digital PLL architecture for ultra low bandwidth applications

Time-based noise-shaping techniques for time-to-digital and analog-to-digital converters

Design techniques for VCO based digital sensor readout circuits

Design techniques for delta sigma modulators using VCO based ADCs