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  • Power efficient H.264 video decoding in embedded multiprocessor

    Creator:
    Kim, Jihong
    Abstract:
    This thesis presents a novel methodology that enables power efficient video decoding in an embedded system based on MPSoC (Multiprocessor System on Chip). This methodology is a physical combination of parallel processing which reduces power consumption of processors by exploiting thread-level parallelism and Dynamic Voltage Frequency Scaling (DVFS) that allows...
    Resource Type:
    Masters Thesis
    Full Text:
    : ______________________________________________________ Ben Lee This thesis presents a novel methodology that enables power efficient video

  • Dependency speculation in dynamic simultaneous multi-threading

    Creator:
    Nelson, Jarrod A.
    Abstract:
    The purpose of this thesis is to explore dependency speculation in Dynamic Simultaneous Multi-Threading (DSMT). DSMT is a microprocessor architecture which attempts to extract Thread Level Parallelism (TLP) from single-threaded programs at run-time. This is accomplished by running multiple iterations of program loops in parallel. The DSMT architecture was originally...
    Resource Type:
    Masters Thesis
    Full Text:
    ? addiu r5, zero, 1 bc1f ELSE ;Branch IF: addiu r17, r17, 1 ;R17 A

  • The dynamic speculation and performance prediction of parallel loops

    Creator:
    Zier, David A.
    Abstract:
    General purpose computer systems have seen increased performance potential through the parallel processing capabilities of multicore processors. Yet this potential performance can only be attained through parallel applications, thus forcing software developers to rethink how everyday applications are designed. The most readily form of Thread Level Parallelism (TLP) within any...
    Resource Type:
    Dissertation
    Full Text:
    within a backward-branch instruction, BPC, and the target PC of the branch, TPC. This definition of a

  • Single-level dynamic register caching architecture for high-performance superscalar processors

    Creator:
    Liebert, John A.
    Abstract:
    The amount of instruction level parallelism (ILP) that can be exploited depends greatly on the size of the instruction window and the number of in-flight instructions the processor can support. However, this requires a register file with a large set of physical registers for renaming and multiple ports to provide...
    Resource Type:
    Masters Thesis
    Full Text:
    AN ABSTRACT OF THE THESIS OF John A. Liebert for the degree of Master of Science in Electrical

  • Designing multimedia extensions for configurable processors

    Creator:
    Zier, David A.
    Abstract:
    The purpose of this thesis is to explore the design of a multimedia extension Instruction Set Architecture (ISA) for a reconfigurable processor. An Extendable Multimedia Module (EM3) was designed as an optional module for X32V. X32V is a prototype configurable processor simulator developed at Oregon State University by John Mark...
    Resource Type:
    Masters Thesis
    Full Text:
    penalty on miss-predicted branch since a 32-bit instruction can span across a memory word and the next

  • Side channel attack resistant elliptic curves cryptosystem on multi-cores for power efficiency

    Creator:
    Yoo, Jaewon
    Abstract:
    The Advent of multi-cores allows programs to be executed much faster than before. Cryptoalgorithms use long-bit words thus parallelizing these operations on multi-cores will achieve significant performance improvement. However, not all long-bit word operations in cryptosystems are suitable for parallel execution on multi-cores. In particular, long-bit words used in Elliptic...
    Resource Type:
    Masters Thesis
    Full Text:
    used (which is one of the recommended word size by NIST) on a quad-core with a 32-bit word size

  • Designing a reconfigurable embedded processor

    Creator:
    Matson, John Mark
    Abstract:
    The growth of applications for embedded processors has spawned a need for highly configurable devices. Custom microprocessors have long life cycles for a fast paced market, where as off-the-shelf designs often do not provide the level of configuration, nor the ability to allow system-on-chip designs. This paper presents a description...
    Resource Type:
    Masters Thesis
    Full Text:
    2) instructions per branch (IPB). PISA branched 19.49% of the time (Table 4) and as a result had

  • A performance study of multithreading

    Creator:
    Kwak, Hantak
    Abstract:
    As the performance gap between processor and memory grows, memory latency will be a major bottleneck in achieving high processor utilization. Multithreading has emerged as one of the most promising and exciting techniques used to tolerate memory latency by exploiting thread-level parallelism. The question however remains as to how effective...
    Resource Type:
    Dissertation
    Full Text:
    generated condition status. Target Registers are used for branch targets, and the computation of a branch

  • Asymmetric clustering using a register cache

    Creator:
    Morrison, Roger Allen
    Abstract:
    Conventional register files spread porting resources uniformly across all registers. This paper proposes a method called Asymmetric Clustering using a Register Cache (ACRC). ACRC utilizes a fast register cache that concentrates valuable register file ports to the most active registers thereby reducing the total register file area and power consumption....
    Resource Type:
    Masters Thesis
    Full Text:
    fast, but can increase the branch misprediction penalty. When a processor incorrectly predicts the

  • A study of hardware/software multithreading

    Creator:
    Carlson, Ryan L.
    Abstract:
    As the design of computers advances, two important trends have surfaced: The exploitation of parallelism and the design against memory latency. Into these two new trends has come the Multithreaded Virtual Processor (MVP). Based on a standard superscalar core, the MVP is able to exploit both Instruction Level Parallelism (ILP)...
    Resource Type:
    Masters Thesis
    Full Text:
    ., branch miss- speculation), sim-outorder introduces the concept of spec_mode. When a conditional branch