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Filtering by: Advisor Mayaram, Kartikeya Remove constraint Advisor: Mayaram, Kartikeya Decade 2000-2009 Remove constraint Decade: 2000-2009 Degree Field Electrical and Computer Engineering Remove constraint Degree Field: Electrical and Computer Engineering

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A comparison of substrate noise coupling in heavily doped and lightly doped substrates...
A comparison of substrate noise coupling in lightly and heavily doped CMOS processes f...
A methodology for efficient substrate noise estimation from large scale digital circui...
A nano-power wake-up circuit for RF energy harvesting wireless sensor networks
A stochastic time-to-digital converter for digital phase-locked loops
A substrate noise coupling model for lightly doped CMOS processes
A test fixture and deembedding procedure for high-frequency substrate characterization
Accurate and efficient simulation of synchronous digital switching noise in system on ...
Algorithms and simulators for coupled device/circuit simulation
Algorithms and tools for optimization of integrated RF VCOs
An efficient and accurate method of estimating substrate noise coupling in heavily dop...
An enhanced swing differential Colpitts CMOS VCO for low-voltage operation
An ultra low power frequency reference for timekeeping applications
An ultra low voltage micropower GPS receiver RF front-end for wildlife tracking
Analysis and design of CMOS RF LNAs with ESD protection
Analysis and modeling of substrate noise coupling for NMOS transistors in heavily dope...
Automated analysis, design, and optimization of low noise oscillators
Comparison and impact of substrate noise due to clocked and clockless circuitry
Comparison of time-domain and frequency-domain phase noise analyses
Computationally efficient substrate noise coupling estimation in lightly doped silicon...
Contributions to substrate noise due to supply coupling and pin parasitics
Coupled circuit and device simulations for design of RF MEMS VCOs
Design techniques for PVT tolerant phase-locked loops
Design techniques for radiation hardened-phase locked loops
Digital phase-locked loops for multi-GHz clock generation
Frequency domain steady-state simulation of oscillators
Ground tap placement and sizing to minimize substrate noise coupling in RF LNAs
Layout dependent and bias independent scalable substrate model for RF MOSFETs
Modeling and simulation methods for RF MEMS VCOs
Oscillators and phase locked loops for space radiation environments
Prediction of phase noise and jitter in ring oscillators
Predictive methodologies for substrate parasitic extraction and modeling in heavily do...
Silencer! : a tool for substrate noise coupling analysis
Simulation and modeling of substrate noise generation from synchronous and asynchronou...
Simulation, measurement, and suppression of digital noise in mixed-signal integrated c...
Steady-state analysis techniques for coupled device and circuit simulation
Substrate coupling macromodel for lightly doped CMOS processes
Substrate noise coupling in ring oscillator-based phase locked loops
Ultra-low energy digital logic controller design for wireless sensor networks