Wireless technologies advance rapidly in the recent time. The maJor initiative is the realization of the third generation wireless network that provides high bandwidth access to digital data on the Internet. Moreover, recent improvements in computer and embedded systems have enabled portable devices with sufficiently high computing capability.
The combination...
NAND flash based solid state drives (SSDs) require out-of-place updating due to the characteristics of flash memories. In addition, due to the mismatched granularity between read/write and erase operations, a cleaning policy involving garbage collection and wear leveling has to perform data migration incurring high overhead. Another challenge is that...
The ubiquity of high quality video and proliferation of mobile devices has contributed to an unprecedented rise in video consumption. HTTP, in conjunction with adaptive streaming, has become the de facto mechanism for delivering the vast majority of video as it readily caters to heterogeneous networks and devices. This dissertation...
Traditional approaches to streaming H.264 video over a network typically rely on a single method of transport (i.e., reliable or unreliable) and/or use static values for parameters that can have a significant negative impact on the perceptual quality of the received video. This dissertation presents a dynamic method for wireless...
Flexible Dual-TCP/UDP Streaming Protocol with Adaptive Bitstream Prioritization (FDSP with Adaptive-BP) is a new method for streaming H.264-encoded High-definition (HD) video over WLANs. Traditionally, video streaming is done either using Transmission Control Protocol (TCP) or User Datagram Protocol (UDP) protocol, resulting in either rebuffering or packet loss respectively. While FDSP-based...
As screen resolution and video decoding capability have increased, high-definition (HD) video in resolutions as high as 1920 x 1080 is rapidly becoming the standard. Ad-hoc streaming of HD video over 802.11 wireless networks, e.g., streaming from a mobile device to a television, is convenient for users, but is hampered...
Wireless High Definition Video Transmission (WHDVT) over 802.11-based networks enjoys widespread deployment among today's multimedia solutions. Examples include Intel® Wireless Display and Apple Airplay®, to name a few. In these systems, peer-to-peer networks are established over which H.264-encoded video is transported wirelessly to be decoded and played back at the...
IO transactions within a computer system have evolved along with other system components (i.e., CPU, memory, video) from programmed IO (PIO). In current mainstream systems (spanning from HPC to mobile) the IO transactions are CPU-centric descriptor-based DMA transactions. The key benefit is that slower IO devices can DMA write system...
High Definition video streaming over WLANs faces many challenges because video data requires not only data integrity but also frames have strict playout deadline. Traditional streaming methods that rely solely on either UDP or TCP have difficulties meeting both requirements because UDP incurs packet loss while TCP incurs delay. This...
The dataflow model of computation differs from the traditional control-flow
model of computation in that it does not utilize a program counter to sequence
instructions in a program. Instead, the execution of instructions is based solely on the
availability of their operands. Thus, an instruction is executed in a dataflow...
There are a number of well known techniques for extracting parallelism from a given program. They range from hardware implementations, building restructuring compilers or reorganizing of programs so as to specify all the available parallelism. The success rate of any of the known techniques is rather poor over all types...
There seems to be a consensus that future Massively Parallel Architectures
will consist of a number nodes, or processors, interconnected by high-speed network.
Using a von Neumann style of processing within the node of a multiprocessor system
has its performance limited by the constraints imposed by the control-flow execution
model....
There appears to be a broad agreement that high-performance computers of the future will be
Massively Parallel Architectures (MPAs), where all processors are interconnected by a high-speed
network. One of the major problems with MPAs is the latency observed for remote operations. One
technique to hide this latency is multithreading....
Efficient routing of messages is critical to the performance of multicomputers. Many adaptive routing algorithms have been proposed to improve the network efficiency; however, they can make only short-sighted decisions to choose a channel for message routing because of limited information about network condition. The short-sighted decisions may cause unnecessary...
Since its introduction in the early 1990s, the quick growth of the World Wide Web
(WWW) traffic raises the question of whether past Local Area Network (LAN) packet
traces still reflect the current situation or whether they have become obsolete. For this
thesis, several LAN packet traces were obtained by...
The multimedia capabilities of computers have recently become the focus of computer developers due to the increasing demand for advanced computer graphics and new media capabilities, such as video conferencing, 3-D visualization, and animation. To support these multimedia capabilities, specialized graphics hardware, such as MPEG encoding/decoding card, 3-D graphics card,...
As the design of computers advances, two important trends have surfaced: The exploitation of parallelism and the design against memory latency. Into these two new trends has come the Multithreaded Virtual Processor (MVP). Based on a standard superscalar core, the MVP is able to exploit both Instruction Level Parallelism (ILP)...
As the performance gap between processor and memory grows, memory latency will be a major bottleneck in achieving high processor utilization. Multithreading has emerged as one of the most promising and exciting techniques used to tolerate memory latency by exploiting thread-level parallelism. The question however remains as to how effective...
In the past, multimedia technology focused mainly on designing high quality audio and graphical imagery as well as providing adequate performance levels that the users demand for multimedia applications. However, the concept of multimedia has expanded into New-Media that involves variety use of multimedia data in consumer-oriented applications, such as...
The microprocessors will have more than a billion logic transistors on a single chip in the near future. Several alternatives have been suggested for obtaining highest performance with billion-transistor chips. To achieve the highest performance possible, an on-chip multiprocessor will become one promising alternative to the current superscalar microprocessor. It...
The AE32000 processor core, developed by Advanced Digital Chips Inc., Korea, is used primarily in the embedded processing environment. The AE32000 simulator models this embedded processor core having high code density. An enhanced simulator was developed to study the performance of the present Instruction Set Architecture after comparison with the...
The growth of applications for embedded processors has spawned a need for highly configurable devices. Custom microprocessors have long life cycles for a fast paced market, where as off-the-shelf designs often do not provide the level of configuration, nor the ability to allow system-on-chip designs. This paper presents a description...
The purpose of this thesis is to explore the design of a multimedia extension Instruction Set Architecture (ISA) for a reconfigurable processor. An Extendable Multimedia Module (EM3) was designed as an optional module for X32V. X32V is a prototype configurable processor simulator developed at Oregon State University by John Mark...
MANETs are known to be useful in situations where mobile nodes need to communicate and coordinate in dynamic environments with no access to fixed network infrastructure. However, connectivity problems can occur when sub-groups within a MANET move out of communication range from one another. The increasingly prolific use of UAVs...
Mobile devices are becoming more prevalent and complex. As a result, the wireless communication aspect of these devices is becoming increasingly significant. At the same time, video demands in terms of availability and quality are also on the uprise. High definition (HD) video is the standard of choice for meeting...
Embedded processors are utilized in many applications with considerable time spent developing and maintaining functionality and performance. Performance being a key factor in adding features such as video and audio to a product. Configurable processors, such as X32V, allow the addition of functionality and performance without large increases in design...
As the number of mobile devices accessing large-scale WLANs such as campus
and metropolitan area networks increases, the need for load balancing among the
cells becomes crucial. In addition, the network must also support some minimum
handoff tolerance defined by an application.
A number of load balancing techniques have been...
A Mobile Ad-hoc NETwork (MANET) is collection of wireless mobile nodes without a network infrastructure or centralized administration. Although MANETs can be used in many applications, such as mobile Internet, military communication, and disaster relief networks, a number of challenges remain. These include routing, medium access control, security, scalability, energy...
This thesis work evaluates the need for a re-configurable cross compiler for the X32V processor architecture and discusses the process of developing a cross compiler for X32V. X32V is a new processor intended at the embedded applications domain whose instruction set is designed based on the widely used MIPS processor....
Rapid advances in wireless networking have led to more mobile phones, PDAs, and other digital mobile devices becoming ubiquitously connected to the Internet. As the demand of delay sensitive real-time applications for these portable devices increases, providing seamless connectivity to wireless networks becomes a critical issue. For this reason, a...
This thesis investigates Dynamic Voltage Scaling (DVS) techniques to lower power consumption in video decoding. A DVS scheme called the Frame-data Computation Aware (FDCA) method has been presented. This method is adaptable not only to stored video applications but also to real-time video scenarios. Unlike DVS schemes for video decoding...
General purpose computer systems have seen increased performance potential through the parallel processing capabilities of multicore processors. Yet this potential performance can only be attained through parallel applications, thus forcing software developers to rethink how everyday applications are designed. The most readily form of Thread Level Parallelism (TLP) within any...
AE32000 microprocessor was developed mainly to address the need for the reduction in the amount of memory accesses in embedded applications. One of the primary goals of a computer architect is the design and construction of machines, that support the efficient execution of the programs that will run on them....
Designing and building a home Media Center can be a daunting task given the multitude of available options and configurations. The goal of this project is to build a home Media Center, and in the process, create a guide that a less technically knowledgeable person could use to build their...
For many years, the von Neumann bottleneck has imposed speed limits on the execution of a program. Because of their sequential nature, von Neumann computers can only execute a single instruction at a time. Instructions that are side-effect free and can be executed in parallel must wait. In an effort...
This thesis presents a novel methodology that enables power efficient video decoding
in an embedded system based on MPSoC (Multiprocessor System on Chip). This
methodology is a physical combination of parallel processing which reduces power
consumption of processors by exploiting thread-level parallelism and Dynamic
Voltage Frequency Scaling (DVFS) that allows...
The Advent of multi-cores allows programs to be executed much faster than before. Cryptoalgorithms use long-bit words thus parallelizing these operations on multi-cores will achieve significant performance improvement. However, not all long-bit word operations in cryptosystems are suitable for parallel execution on multi-cores. In particular, long-bit words used in Elliptic...
Wireless Networks have been widely adopted into a major part of today's network infrastructure. They have become a popular technology to not only expand the coverage of wired networks but also to interconnect a large wireless network, i.e., wireless mesh networks. As they allow more flexible communication than traditional wired-networks...
The purpose of this thesis is to explore methods which can reduce the power dissipation of a mobile system while decoding MPEG video. MPEG decoding is a microprocessor intensive process that makes heavy use of both the L1 and L2 caches as well as main memory. The heavy load placed...
Dynamic multithreaded processors attempt to increase the performance of a single
sequential program by dynamically extracting threads from sources such as loop
iterations. The scheduling of instructions in such a processor plays a vital role in the
amount of thread level parallelism that can be extracted and thus the overall...
The amount of instruction level parallelism (ILP) that can be exploited depends
greatly on the size of the instruction window and the number of in-flight instructions
the processor can support. However, this requires a register file with a large set of
physical registers for renaming and multiple ports to provide...
Conventional register files spread porting resources uniformly across all registers. This paper proposes a method called Asymmetric Clustering using a Register Cache (ACRC). ACRC utilizes a fast register cache that concentrates valuable register file ports to the most active registers thereby reducing the total register file area and power consumption....
The purpose of this thesis is to explore dependency speculation in Dynamic Simultaneous Multi-Threading (DSMT). DSMT is a microprocessor architecture which attempts to extract Thread Level Parallelism (TLP) from single-threaded programs at run-time. This is accomplished by running multiple iterations of program loops in parallel. The DSMT architecture was originally...